PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.4. I/O Standards

The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 84.  I/O Standards and Termination Values for Intel® Arria® 10 Devices
I/O Standard Valid Input Terminations (Ω) 12 Valid Output Calibrated/Uncalibrated Terminations (Ω)12 RZQ (Ω) 13 Differential/Complementary I/O Support
SSTL-12 14 60, 120 40, 60 240 Yes
SSTL-125 14 60, 120 34, 40 240 Yes
SSTL-135 14 60, 120 34, 40 240 Yes
SSTL-15 14 60, 120 34, 40 240 Yes
SSTL-15 Class I 15 0, 50 0, 50 100 Yes
SSTL-15 Class II15 0, 50 0, 25 100 Yes
SSTL-18 Class I15 0, 50 0, 50 100 Yes
SSTL-18 Class II15 0, 50 0, 25 100 Yes
1.2-V HSTL Class I15 0, 50 0, 50 100 Yes
1.2-V HSTL Class II15 0, 50 0, 25 100 Yes
1.5-V HSTL Class I15 0, 50 0, 50 100 Yes
1.5-V HSTL Class II15 0, 50 0, 25 100 Yes
1.8-V HSTL Class I15 0, 50 0, 50 100 Yes
1.8-V HSTL Class II15 0, 50 0, 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No
Table 85.  I/O Standards and Termination Values for Intel® Cyclone® 10 GX Devices
I/O Standard Valid Input Terminations (Ω) 12 Valid Output Calibrated/Uncalibrated Terminations (Ω)12 RZQ (Ω) 13 Differential/Complementary I/O Support
SSTL-12 16 60, 120 40, 60 240 Yes
SSTL-125 16 60, 120 34, 40 240 Yes
SSTL-135 16 60, 120 34, 40 240 Yes
SSTL-15 16 60, 120 34, 40 240 Yes
SSTL-15 Class I 17 0, 50 0, 50 100 Yes
SSTL-15 Class II17 0, 50 0, 25 100 Yes
SSTL-18 Class I17 0, 50 0, 50 100 Yes
SSTL-18 Class II17 0, 50 0, 25 100 Yes
1.2-V HSTL Class I17 0, 50 0, 50 100 Yes
1.2-V HSTL Class II17 0, 50 0, 25 100 Yes
1.5-V HSTL Class I17 0, 50 0, 50 100 Yes
1.5-V HSTL Class II17 0, 50 0, 25 100 Yes
1.8-V HSTL Class I17 0, 50 0, 50 100 Yes
1.8-V HSTL Class II17 0, 50 0, 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No
12 0 is equivalent to no termination.
13 RZQ pin is not required for uncalibrated output terminations.
14 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
15 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.
16 Use this I/O standard if input termination is required with interface frequency more than 533 MHz.
17 Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.

Did you find the information on this page useful?

Characters remaining:

Feedback Message