PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

3.2.5.4. Calibration Guidelines

The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP allows you to dynamically reconfigure the features of the interface. However, performing calibration is an application specific process. This section provides some general guidelines for calibrating Intel® Stratix® 10 I/O architecture.

Note: Follow the guidelines when generating your own dynamic reconfiguration controller.

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