PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

3.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 48.  I/O Standards and Termination Values
I/O Standard Valid Input Terminations (Ω) Valid Output Terminations (Ω) RZQ (Ω) Differential/Complementary I/O Support
Important:
PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP does not support differential data pins.
SSTL-12 60, 120 40, 60,240 240 Yes
SSTL-125 40, 60, 120 34, 40 240 Yes
SSTL-135 40, 60, 120 34, 40 240 Yes
SSTL-15 40, 60, 120 34, 40 240 Yes
SSTL-15 Class I 50 50 100 Yes
SSTL-15 Class II 50 25 100 Yes
SSTL-18 Class I 50 50 100 Yes
SSTL-18 Class II 50 25 100 Yes
1.2-V HSTL Class I 50 50 100 Yes
1.2-V HSTL Class II 50 25 100 Yes
1.5-V HSTL Class I 50 50 100 Yes
1.5-V HSTL Class II 50 25 100 Yes
1.8-V HSTL Class I 50 50 100 Yes
1.8-V HSTL Class II 50 25 100 Yes
1.2-V POD 34, 40, 48, 60, 80, 120, 240 34, 40, 48, 60 240 Yes
1.2-V No
1.5-V No
1.8-V No

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