220.127.116.11.2. Generate the Simulation Design Example
The make_sim_design.tcl generates a simulation design example and tool-specific scripts to compile and elaborate the necessary files.
To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:
quartus_sh -t make_sim_design.tcl VERILOG
To generate the design example for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL
This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation using the corresponding tool.
The simulation design example provides a generic example of the core and I/O connectivity for your IP configuration. Functionally, the simulation triggers read and write operations over each group in your configured IP. The following diagram shows a simple one group PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP instantiation in the testbench.