PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP 3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Guidelines 2.6. Design Example
2.2. Functional Description
2.2.1. Intel® Agilex™ I/O Sub-bank Interconnects 2.2.2. Intel® Agilex™ Input DQS/Strobe Tree 2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces 2.2.4. Dynamic Reconfiguration 2.2.5. I/O Timing
2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces
2.2.3.1. Clocks 2.2.3.2. Output Path 2.2.3.3. Input Path
2.2.3.1. Clocks
2.2.3.1.1. Clock Frequency Relationships
2.2.4. Dynamic Reconfiguration
2.2.4.1. Connectivity 2.2.4.2. Reconfiguration Features and Register Addressing 2.2.4.3. Dynamic Reconfiguration Guidelines
2.2.4.2. Reconfiguration Features and Register Addressing
2.2.4.2.1. Control Registers Addresses 2.2.4.2.2. Control Registers
2.2.4.3. Dynamic Reconfiguration Guidelines
2.2.4.3.1. Strobe Enable Window Calibration 2.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 2.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
2.3. Getting Started
2.3.1. Parameter Settings 2.3.2. Signals
2.3.1. Parameter Settings
2.3.1.1. Read Latency 2.3.1.2. Write Latency
2.3.2. Signals
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards
2.4.1. Input Buffer Reference Voltage (VREF) 2.4.2. On-Chip Termination (OCT)
2.4.2. On-Chip Termination (OCT)
2.4.2.1. RZQ_GROUP Assignment
2.5. Design Guidelines
2.5.1. Guidelines: Group Pin Placement 2.5.2. Reference Clock 2.5.3. Reset
2.6. Design Example
2.6.1. Generate the Design Example
2.6.1. Generate the Design Example
2.6.1.1. Design Example without Dynamic Reconfiguration 2.6.1.2. Dynamic Reconfiguration Design Examples
2.6.1.1. Design Example without Dynamic Reconfiguration
2.6.1.1.1. Generate the Synthesis Design Example 2.6.1.1.2. Generate the Simulation Design Example
2.6.1.2. Dynamic Reconfiguration Design Examples
2.6.1.2.1. Generate the Synthesis Design Example 2.6.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description
3.2.1. Top Level Interfaces 3.2.2. Clocks 3.2.3. Output Path 3.2.4. Input Path 3.2.5. Dynamic Reconfiguration
3.2.2. Clocks
3.2.2.1. Clock Frequency Relationships
3.2.3. Output Path
3.2.3.1. Output Path Data Alignment
3.2.4. Input Path
3.2.4.1. Input Path Data Alignment
3.2.5. Dynamic Reconfiguration
3.2.5.1. RTL Connectivity 3.2.5.2. Address Lookup 3.2.5.3. Reconfiguration Features and Register Addressing 3.2.5.4. Calibration Guidelines
3.2.5.1. RTL Connectivity
3.2.5.1.1. Daisy Chain
3.2.5.2. Address Lookup
3.2.5.2.1. Strobes 3.2.5.2.2. Parameter Table Examples
3.2.5.3. Reconfiguration Features and Register Addressing
3.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 3.2.5.3.2. Control Registers Description
3.2.5.4. Calibration Guidelines
3.2.5.4.1. Strobe Enable Window Calibration 3.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
3.3. Getting Started
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals 3.3.2.4. Avalon Configuration Bus Interface Signals 3.3.2.5. Termination Signals
3.4. I/O Standards
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.1. Input Buffer Reference Voltage (VREF)
3.4.1.1. Calibrated VREF Settings
3.4.2. On-Chip Termination (OCT)
3.4.2.1. RZQ_GROUP Assignment 3.4.2.2. Manual Insertion of OCT Block
3.5. Design Guidelines
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset 3.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 3.5.5. Dynamic Reconfiguration 3.5.6. Timing
3.5.6. Timing
3.5.6.1. Timing Components 3.5.6.2. Timing Constraints and Files 3.5.6.3. Timing Analysis 3.5.6.4. Timing Closure Guidelines
3.5.6.2. Timing Constraints and Files
3.5.6.2.1. .sdc 3.5.6.2.2. _parameter.tcl 3.5.6.2.3. _ip_parameters.tcl 3.5.6.2.4. _pin_map.tcl 3.5.6.2.5. _report_timing.tcl 3.5.6.2.6. _report_timing_core.tcl
3.5.6.4. Timing Closure Guidelines
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration 3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 3.5.6.4.5. I/O Timing Violation 3.5.6.4.6. Internal FPGA Path Timing Violation
3.6. Design Example
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration
3.6.1.1.1. Generate the Hardware Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example 4.7. Application Specific Design Example
4.2. Functional Description
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF)
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT)
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files
4.5.6.2.1. .sdc 4.5.6.2.2. _parameter.tcl 4.5.6.2.3. _ip_parameters.tcl 4.5.6.2.4. _pin_map.tcl 4.5.6.2.5. _report_timing.tcl 4.5.6.2.6. _report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.2.1. Dynamic Reconfiguration with Debug Kit 4.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
4.7. Application Specific Design Example
4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

3.5.6.3. Timing Analysis

Table 53.  Timing AnalysisThis table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces IP.
Location Description
I/O The PHY Lite for Parallel Interfaces IP generation creates the appropriate generated clock settings for the read strobe on the read path and the write strobe of the write path, according to their strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the following format:
  • Clock name for read strobe—<pin_name>_IN.
  • Clock name for the write path—<pin_name> for positive strobe.
  • Clock name for the write path—<pin_name>_neg for negative strobe.
The set_false_path, set_input_delay and set_output_delay constraints are also generated to ensure proper timing analysis of the PHY Lite for Parallel Interfaces IP.
FPGA The PHY Lite for Parallel Interfaces IP generation creates the clock settings for the user core clock and the periphery clock in the following formats:
  • user core clock— <variation_name>_usr_clk
  • periphery clock— <variation_name>_phy_clk*

The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel Interfaces IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing of this IP interface transfer and within core transfer correctly.

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