PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.6.1.1.1. Generate the Hardware Design Example

The make_qii_design.tcl generates a synthesizable hardware design example along with a Quartus project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following script:

quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project with the Intel® Quartus® Prime software.

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