PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.2. Functional Description

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP utilizes the I/O banks in Intel® Agilex™ devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.

Each each sub-bank contains the following components:

  • Hard memory controller
  • I/O PLL and PHY clock trees
  • DLL
  • Input DQS/strobe trees
  • 48 pins, organized into four I/O lanes of 12 pins each
Figure 1.  I/O Bank Structure (Die Top View)This figure shows the I/O bank structure of the device. The figure shows the view of the die, as shown in the Intel® Quartus® Prime Chip Planner. In the Pin Planner, the view is flipped. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks and the locations of the SDM and HPS shared I/O banks for each device package.

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