2.2. Functional Description
The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP utilizes the I/O banks in Intel® Agilex™ devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.
Each each sub-bank contains the following components:
- Hard memory controller
- I/O PLL and PHY clock trees
- Input DQS/strobe trees
- 48 pins, organized into four I/O lanes of 12 pins each
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