PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.3.1.1. Read Latency

Table 13.  Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock Cycle)
Quarter rate 1 7
2 7
4 7
8 7

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