PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Document Table of Contents Reconfiguration Features and Register Addressing

Each reconfigurable feature of the interface has a set of control registers with an associated memory address to store the reconfigurable settings; however, this address is placement dependent.

The following two sets of control registers store the reconfiguration feature settings:

  • Control/status registers (CSR)—You can only read the values of these registers. The values are set through the IP parameters. The CSR registers contain the default setting in the IP.
  • Avalon® memory-mapped registers—You can read and write to these registers using Avalon® interface. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.

Did you find the information on this page useful?

Characters remaining:

Feedback Message