PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP

You can configure the PHY Lite for Parallel Interfaces IP to support multiple groups (maximum 48 I/O pins each).

The following lists the possible implementations:

  • Instantiates one PHY Lite for Parallel Interfaces IP with two groups
    • Bidirectional type for DQ and DQS signals
    • Output type for Addr/Cmd signals
Note: Each group in the PHY Lite for Parallel Interfaces IP can have 48 I/Os, and the IP supports up to 18 groups.
Figure 91.  General Tab Settings


Figure 92.  Group 0 settings (Bidirectional type for DQ and DQS)


Figure 93.  Group 1 settings (Output type for Addr/Cmd)


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