4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
You can configure the PHY Lite for Parallel Interfaces IP to support multiple groups (maximum 48 I/O pins each).
The following lists the possible implementations:
- Instantiates one PHY Lite for Parallel Interfaces IP with two groups
- Bidirectional type for DQ and DQS signals
- Output type for Addr/Cmd signals
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