2.2.4. Dynamic Reconfiguration
You must perform calibration to achieve timing closure at a high frequency because of the asynchronous nature of the PHY. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP, you can perform calibration using the dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify the input and output delays by writing to a set of control registers using an Avalon® memory-mapped interface.
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