Visible to Intel only — GUID: sum1554087119514
Ixiasoft
Visible to Intel only — GUID: sum1554087119514
Ixiasoft
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
Two instances of PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopback using a custom HiLo loopback card on the Intel® Stratix® 10 GX FPGA development kit. One PHY Lite instance is configured as a transmitter (DUT_OUTPUT) and the other PHY Lite instance is configured as a receiver (DUT_INPUT).
Section Content
Features
Hardware and Software Requirements
Design System Architecture Overview
Dynamic Reconfiguration Overview
PHY Lite Per-Bit Overview
Compiling the Reference Design
Hardware Testing
Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Stratix 10 Devices
Appendix A: HiLo Loopback Card Pin Connections
Appendix B: Retrieving Lane and Pin Information
Appendix C: Decoding Parameter Table
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