1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
Two instances of PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopback using a custom HiLo loopback card on the Intel® Stratix® 10 GX FPGA development kit. One PHY Lite instance is configured as a transmitter (DUT_OUTPUT) and the other PHY Lite instance is configured as a receiver (DUT_INPUT).