AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
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1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

The PHY Lite for Parallel Interfaces reference design demonstrates the usage of the dynamic reconfiguration feature using the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core.

Two instances of PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. These PHY Lite instances are loopback using a custom HiLo loopback card on the Intel® Stratix® 10 GX FPGA development kit. One PHY Lite instance is configured as a transmitter (DUT_OUTPUT) and the other PHY Lite instance is configured as a receiver (DUT_INPUT).

Figure 1. Block Diagram—PHY Lite for Parallel Interfaces Reference Design System for Intel® Stratix® 10 Devices
Note: For the HiLo loopback card pin connections, refer to Appendix A: HiLo Loopback Card Pin Connections. For more information about the HiLo loopback card, contact Intel® Support.