AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents

1.4. Dynamic Reconfiguration Overview

Dynamic reconfiguration reconfigures the input and output delays in the PHY Lite for Parallel Interfaces IP core.

This feature allows you to perform real-time configuration on the delay of DQS/Strobe or DQ/data signals. This feature helps to maximize the data valid window, allowing the design to achieve timing closure at high frequency. You can turn on Use dynamic reconfiguration in the parameter editor of the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core in Intel® Quartus® Prime Pro Edition software and the reconfiguration is performed via the Avalon® -MM interface.