AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents

1.10. Appendix B: Retrieving Lane and Pin Information

Information about each IP instance is stored in the I/O SSM named as parameter table.
You can access the parameter table via Avalon® interface at the base address offset 0x5000000 . The global parameter table lists all interfaces in the I/O column. Once the lane and pin addresses of the target PHY Lite for Parallel Interfaces interface is captured, the target pin can get reconfigured by Read/Write through calibration address offset of 0x3000000 . The base address offset, parameter table size offset, and interface offset are fixed, as defined in an algorithm shown in the following figure:
Figure 22. Flow Chart of Reading Parameter Table

The code block below is written in Nios® II processor to read out the parameter table as shown in Figure 23.

#define BASE_ADDR           0x5000000
#define PT_SIZE_PTR         0x0000014
#define ADDR_OFFSET         0x0000024
void Read_Param_table()
  int delay = -1;
  int addr_offset = -1;
  unsigned int size = 0;
  unsigned int value = 0;
  int i;

addr_offset = IORD32(BASE_ADDR+ADDR_OFFSET);
printf("Reading Addr Offset from Param Table: %08x\n\n",addr_offset);
printf("Param Table size is %08x:\n", size);
printf("\nParam Table:\n");
for (addr=0x0; addr < size+1; addr += 4) {
value =  IORD32(BASE_ADDR+addr);