AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents Traffic Generator/Checker Module

The traffic generator/checker module is responsible for transmitting data to DUT_OUTPUT and receiving data from DUT_INPUT during normal operating mode.

The transmitted data is random data generated by the Linear Feedback Shift Register (LFSR). The received data from DUT_INPUT should match with the transmitted data for result comparison.