AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

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ID 683220
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

1.7.2. Generating Executable and Linking Format (.elf) Programming File

Follow the steps below to generate an executable and linking format (.elf) programming file. These steps are necessary if you would like to modify the phylite_dynamic_reconfiguration.c, phylite_dynamic_reconfiguration.h and hello_world.c files.

  1. In the Intel® Quartus® Prime Pro Edition software version 19.1, select Tools > Nios® II Software Build Tools for Eclipse.
    Figure 14.  Nios® II Software Build Tools for Eclipse
  2. Create a new workspace when the Select a workspace window prompt appears.
    Figure 15. Create New Workspace
  3. Select File > New > Nios® II Application and BSP from Template in the Nios II - Eclipse window.
    Figure 16.  Nios® II Application and BSP from Template
  4. In the SOPC Information File name parameter, browse to the location of phylite_nios.sopcinfo file in your host machine. Click OK to select the file and Eclipse automatically loads all CPU settings.
    The phylite_nios.sopcinfo is created when generating phylite_nios.qsys.
  5. In the Project name parameter, specify your desired project name.
  6. Choose Hello World as the project template.
  7. Click Finish to generate the project. The Intel® Quartus® Prime Pro Edition software creates a new directory named software in the specified project location.
    Figure 17.  Nios® II Application and BSP from Template Settings
  8. Replace the following files from <project directory>/software reference design with the files located in your new software directory.
    • hello_world.c
    • phylite_dynamic_reconfiguration.c
    • phylite_dynamic_reconfiguration.h
  9. In the Nios II - Eclipse window, press F5 to refresh the window and reload the new files into the project.
  10. Click Project > Build Project.
  11. Make sure the <project_name>.elf file is generated in the new <project directory>/software/<project_name>/ directory.
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