AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

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ID 683220
Date 9/11/2020
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Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

1.5.2. Read Deskew Algorithm

The PHY Lite for Parallel Interfaces IP core does not come with any calibration engine or calibration algorithm.

The read deskew algorithm gives an idea how you can write any calibration algorithm to get an optimal margin of capturing data by center aligning DQS to all DQ. This algorithm calibrates the following knobs on input PHY Lite for Parallel Interfaces side.

Table 2.  Knob Step Size
Knob Unit Per Step
DQSen delay 1 external interface clock cycle.
DQSen phase 1/128th VCO clock cycle.
Input DQS 1/256th VCO clock cycle.
Input per-bit DQ 1/256th VCO clock cycle.
This algorithm consists of three steps:
  1. DQSen Calibration
    • Sweep through DQSen (delay + phase) settings from min to max 
      for (cur_delay = PIN_DQS_EN_DLY_DLY_VAL_MIN; cur_dly <=
PIN_DQS_EN_DLY_DLY_VAL_MAX; cur_dly++) {
    for (cur_phase = PIN_DQS_EN_PHASE_DLY_VAL_MIN; cur_phase <= PIN_DQS_EN_PHASE_DLY_VAL_MAX; cur_phase++) {
    //More code goes here
    }
}
    • For each iteration, send 5 separate patterns on each pin to compare.
    • Find passing window width.
    • Set DQSen delay and DQSen phase of passing window to center.
  2. Per-bit DQ Deskew
    • Sweep individual dq_input_delay to find both right and left edge.
    • Set per-bit DQ to its center ((left edge + right edge)/2).
  3. DQS Deskew
    • Sweep dqs_input_delay from high to low.
    • Find passing window width and set DQS to center.
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