AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents

1.5. PHY Lite Per-Bit Overview

The PHY Lite for Parallel Interfaces IP core has the per-bit calibration capability that is used to calibrate each DQ pin delay to achieve maximum performance.

When a large amount of DQ pins are used on high-speed transfer, it is very likely that most of the DQ have a narrower passing window. This limits the maximum performance of the system, as well as having the possibility of data corruption.