AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents DYN_CFG Controller

The DYN_CFG controller module consists of a Nios® II processor that acts as a centralized controller that handles the configuration of the PHY Lite for Parallel Interfaces IP core via Avalon® interface and handles control signals through parallel I/O modules.

The DYN_CFG controller module performs address translation to retrieve the physical address of the strobe or data pin to be configured. This module has forward and reverse paths. In the forward path, this module transmits data to the DUT_OUTPUT module. In the reverse path, this module receives data from the DUT_INPUT module.

Dynamic reconfiguration code is written in the Nios® II Software Build Tools for Eclipse and loaded into the instruction memory of the soft Nios® II processor. The Nios® II processor executes this code to perform calibrations. During processing, the Nios® II processor writes to the register in the I/O subsystem manager (I/O SSM) to change the DQS/DQ delay. Once the calibration is done and the data valid window is found, the Nios® II processor sets cfg_done to 1 and the interface to the IP core switches to the traffic generator. The traffic generator begins generating random data pattern and checks against the loopback data that comes back from the IP core input.