AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents

1.3. Design System Architecture Overview

This reference design consists of a calibration engine (phylite_nios.qsys) and PHY Lite for Parallel Interfaces IP core instances (dut_INPUT.qsys and dut_OUTPUT.qsys) for data loopback and other functional blocks.

You can use this reference design as a starting point design and modify as required to suit your design application.

Figure 2. Block Diagram—PHY Lite for Parallel Interfaces Design System Architecture

The reference design consists of:

  • Traffic generator/checker module
  • DYN_CFG Controller
  • Clocking Scheme