PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
Public

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Document Table of Contents

1. About the PHY Lite for Parallel Interfaces IP

Updated for:
Intel® Quartus® Prime Design Suite 21.4

This user guide describes the following IPs:

  • PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP
  • PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
  • PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
  • PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX FPGA IP cores

The PHY Lite for Parallel Interfaces IP core is primarily used for building custom memory interface PHY blocks. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (Synchronous Mode), and Mobile DDR. The PHY Lite for Parallel Interfaces IP is suitable for simple parallel interfaces with single-ended I/O.

The IP has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorter which yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance.

This IP controls the strobe-based capture I/O elements. Each instance of the IP can support an interface up to 18 individual data/strobe capture groups. Each group can contain up to 48 data I/Os as well as the strobe capture logic.

In addition, this IP supports Dynamic Reconfiguration feature which enables reconfiguration of the data and strobe delays. You can align the data and strobe via calibration to achieve timing closure at high frequencies.

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