PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

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Document Table of Contents Daisy Chain

The I/O column provides a single physical Avalon memory-mapped interface. All IP in the I/O column that require Avalon memory-mapped interface access the same physical Avalon memory-mapped interface. The system-level RTL for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfigurable IPs in an I/O column.

For PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP and PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX FPGA IPs, the Avalon memory-mapped address is 28 bits where the top 4-bits are the ID of the interface to be addressed in the daisy chain. These bits are only required for the daisy chain arbitration in RTL simulation, so they are not synthesized during compilation. If only one interface is addressed from the IP, it is sufficient to connect these bits as the interface’s ID.

Figure 70. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite for Parallel Interfaces IP before and after placement.

Notice that all core controllers must go through the arbitration logic that you created in the FPGA core logic to connect to an interface on the daisy chain. The end of the daisy chain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon address pins during compilation, therefore use the postfit netlist for proper simulation of the merged I/O column instead of prefit netlist.