PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
Public

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3.3.1.1. Read Latency

Table 40.  Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Read Latency (External Memory Clock Cycle)
Full rate 1 4
2 4
4 3
8 3
Half rate 1 5
2 5
4 4
8 4
Quarter rate 1 7
2 7
4 7
8 7

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