PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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3.5.1. Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP group pins.
  1. All groups in a PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group.
  2. Two groups, from either the same or different PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP, cannot share an I/O lane.
  3. For PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP instance that spans more than one I/O bank, all groups in the interface must be placed across a contiguous set of banks within an I/O column. The number of I/O banks required depends on the memory interface width.
  4. Pins that are not used in an I/O bank are available as general purpose I/O (GPIO) pins.
  5. To constrain groups from separate PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies, and the same voltage settings.
  6. A reference clock network can only span across maximum of 6 I/O banks.
  7. You cannot share the OCT termination block across the I/O column. You can associate the terminated pins of the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP instance with an RZQ pin through RZQ_GROUP assignment.
Table 51.  Group Pin Placement PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP does not support DQS for X4.
Number of Pins in Group Valid DQS Group in a Bank Valid Index in a Bank
1-12 DQS for X8/X9 {0-11}/{12-23}/{24-35}/{36-47}
13-24 DQS for X16/X18 {0-23}/{24-47}
25-48 DQS for X32/X36 {0-47}

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