PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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3.2.2. Clocks

The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.

Table 23.   PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP Clock Domains
Clock Domain Description
Core clock This clock is generated internally by the IP and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock This clock is used internally by the IP for PHY circuitry running at the same frequency as the core clock.
VCO clock This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator.
Interface clock This is the clock frequency of the external device connected to the FPGA I/Os.
Table 24.   PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP Supported Interface FrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of the core clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of 800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.
Core Clock Rate Speed Grade –1 (MHz) Speed Grade –2 (MHz) Speed Grade –3 (MHz)
Min Max Min Max Min Max
Full 100 333 100 300 100 233
Half 100 667 100 600 100 467
Quarter 100 1200 100 1200 100 933

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