The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.
|Core clock||This clock is generated internally by the IP and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers.|
|PHY clock||This clock is used internally by the IP for PHY circuitry running at the same frequency as the core clock.|
|VCO clock||This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator.|
|Interface clock||This is the clock frequency of the external device connected to the FPGA I/Os.|
|Core Clock Rate||Speed Grade –1 (MHz)||Speed Grade –2 (MHz)||Speed Grade –3 (MHz)|
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