PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
Public

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4.3.1.2. Write Latency

Table 77.  Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Write Latency (External Memory Clock Cycle)
Full rate 1 0
2 0
4 0
8 0
Half rate 1 1
2 1
4 1
8 1
Quarter rate 1 3
2 3
4 3
8 2

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