PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Output Path Data Alignment

The group_data_from_core and group_oe_from_core signals are arranged in time slices, which are separated into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP.

Example of time slices with individual pins correlation:

{time(n),time(n-1),time(n-2),... time(0)}

Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}

The following figure shows how data from group_<X>_data_from_core are written on the group_<X>_data_io relative to group_<X>_strobe_io.

Note that group_<X>_strobe_io is in tristate outside data valid window.

Figure 11. Example Output for Quarter Rate DDR

Did you find the information on this page useful?

Characters remaining:

Feedback Message