PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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2.6.1.2.1. Generate the Synthesis Design Example

The make_qii_design.tcl generates a synthesizable hardware design example and an Intel® Quartus® Prime project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IP generation:
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:
quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project using the Intel® Quartus® Prime software.

The synthesis design example provides an example of the core and I/O connectivity for your IP configuration with Calibration IP as the interface for the Avalon® memory-mapped calibration addresses. The connection of Calibration IP to PHY Lite for Parallel Interfaces IP is limited to one calibration IP per row.

Figure 24. Connection of Calibration IP to PHY Lite for Parallel Interfaces IPThis figure shows an example of multiple (five in this example) PHY Lite for Parallel Interfaces IPs within one I/O row. Thus, only one calibration IP is needed to connect all five PHY Lite for Parallel Interfaces IPs to the Calibration IP.
Note: Follow the guidelines described in the Dynamic Reconfiguration Guidelines section when generating your own dynamic reconfiguration controller.

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