126.96.36.199.1. Generate the Synthesis Design Example
The make_qii_design.tcl generates a synthesizable hardware design example and an Intel® Quartus® Prime project, ready for compilation.
quartus_sh -t make_qii_design.tcl
quartus_sh -t make_qii_design.tcl [device_name]
This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project using the Intel® Quartus® Prime software.
The synthesis design example provides an example of the core and I/O connectivity for your IP configuration with Calibration IP as the interface for the Avalon® memory-mapped calibration addresses. The connection of Calibration IP to PHY Lite for Parallel Interfaces IP is limited to one calibration IP per row.
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