PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

Download
ID 683716
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7. Application Specific Design Example

This design example demonstrates the PHY Lite for Parallel Interfaces IP implementation for a NAND Flash design in Intel® Arria® 10 devices.

The following figure shows the RTL view of the design example.

Figure 93.  RTL Viewer for a NAND Flash Simple Design Based on the PHY Lite for Parallel Interfaces IP

Did you find the information on this page useful?

Characters remaining:

Feedback Message