You can find the location of the <variation_name> .sdc file in the .qip or .qsys, which is generated during the IP generation. The <variation_name> .sdc allows the Fitter to optimize timing margins with timing driven compilation and allows the Timing Analyzer to analyze the timing of your design.
The IP uses <variation_name> .sdc for the following operations:
- Creating clocks on PLL inputs
- Creating generated clocks
- Calling derive_clock_uncertainty
- Creating set_output_delay and set_input_delay constraints to analyze the timing of the read and write paths
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