2.2.1. Intel® Agilex™ I/O Sub-bank Interconnects
There are interconnects between the sub-banks which chain the sub-banks into a row. The following figures show how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in various Intel® Agilex™ device variants. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package. Each sub-bank is labeled with ID number to facilitate pin placement.