PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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2.2.1. Intel® Agilex™ I/O Sub-bank Interconnects

There are interconnects between the sub-banks which chain the sub-banks into a row. The following figures show how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in various Intel® Agilex™ device variants. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package. Each sub-bank is labeled with ID number to facilitate pin placement.

Figure 2. Sub-bank Ordering with ID in Top I/O Row in Intel® Agilex™ AGF012 and AGF014, Package R24B
Figure 3. Sub-bank Ordering with ID in Bottom I/O Row in Intel® Agilex™ AGF012 and AGF014, Package R24B
Figure 4. Sub-bank Ordering with ID in Top I/O Row in Intel® Agilex™ AGF014, Package R24C
Figure 5. Sub-bank Ordering with ID in Bottom I/O Row in Intel® Agilex™ AGF014, Package R24C
Figure 6. Sub-bank Ordering with ID in Top I/O Row in Intel® Agilex™ AGF022 and AGF027 Devices, Package R25A
Figure 7. Sub-bank Ordering with ID in Bottom I/O Row in Intel® Agilex™ AGF022 and AGF027 Devices, Package R25A

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