PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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3.4.1. Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>
Note: The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings (including GPIOs).
Table 49.  VREF_MODE Description
VREF Mode Description
EXTERNAL Use the external VREF. This is the default.
CALIBRATED Use internal VREF generated using VREF codes from the Avalon memory-mapped reconfiguration bus.
VCCIO_45 Use internal VREF generated using static VREF code. VREF is 45% of VCCIO
VCCIO_50 Use internal VREF generated using static VREF code. VREF is 50% of VCCIO
VCCIO_55 Use internal VREF generated using static VREF code. VREF is 55% of VCCIO
VCCIO_65 Use internal VREF generated using static VREF code. VREF is 65% of VCCIO
VCCIO_70 Use internal VREF generated using static VREF code. VREF is 70% of VCCIO
VCCIO_75 Use internal VREF generated using static VREF code. VREF is 75% of VCCIO
Figure 46. VREF


Note: You must select the VREF range for your design using analog simulation.

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