2.5.1. Guidelines: Group Pin Placement
- All groups in a PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group. Refer to the Intel® Agilex™ Input DQS Clock Tree for more information about the number lanes used per pin width.
- A PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP must fit within one I/O sub-bank and must not span across multiple I/O sub-banks. One I/O sub-bank can support only one IP instance.
- Two groups within a PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP cannot share an I/O lane.
- When there are multiple groups within an IP instance, the pins must be set to either bidirectional or unidirectional (can be a mix of input and output groups). Do not mix bidirectional and unidirectional pin types in the same IP instance.
- If an input group uses ×36 DQS/strobe tree, another group must be set as an output group to utilize the remainder I/O lane in the same I/O sub-bank.
- If a group is set to bidirectional pin type and uses the ×36 DQS/strobe tree, no other groups are allowed to be in the same IP.
- Control signals are shared across all groups within an IP instance.
- Pins that are not used in an I/O sub-bank cannot be used as GPIO pins.
- You must calibrate the I/Os within the same I/O lane using the same OCT calibration block. You can associate the terminated pins of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP instance with an RZQ pin through the RZQ_GROUP assignment.
- You can place the data pin locations either automatically or manually in the Pin Placement tab. You must enter your desired Physical Sub-Bank ID. Refer to diagrams in the Intel® Agilex™ I/O Sub-bank Interconnects topic for the physical sub-bank ID for pin placement.
- The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP must be placed at the Quartus-IP Generation stage because the pin placements are not available using QSF Assignments.
|I/O Bank Pin Index||I/O Sub-bank Pin Index||Lane||Sub-bank Location|
|0-11||0-11 (pins 4 and 5 are reserved for strobes)||0||Bottom|
|12-23||12-23 (pins 16 and 17 are reserved for strobes)||1|
|24-35||24-35 (pins 28 and 29 are reserved for strobes)||2|
|36-47||36-47 (pins 40 and 41 are reserved for strobes)||3|
|48-59||0-11 (pins 4 and 5 are reserved for strobes)||0||Top|
|60-71||12-23 (pins 16 and 17 are reserved for strobes)||1|
|72-83||24-35 (pins 28 and 29 are reserved for strobes)||2|
|84-95||36-47 (pins 40 and 41 are reserved for strobes)||3|
For more information about strobe and clock pin indexes, refer to the device pin-out files.
Automatic and Manual Pin Placement
Follow these guidelines for automatic and manual pin placements:
- Go to the Pin Placement tab.
- To identify the sub-bank:
Figure 20. Example of Pin Placement for a Single Group
- Default value = 0.
- Use only bonded sub-banks. The bonded sub-banks are unshaded in the Example of Pin Placement for a Single Group diagram.
- This example uses sub-bank ID =1 that is located at Bank 3A.
This example uses the Intel® Agilex™ AGF022 and AGF027 devices, package R25A.
- Each sub-bank has 48 pins.
- In automatic mode, by default, all pins inside a group are placed in a tightly packed manner.
- In manual mode, you can customize the pin placement within the sub-bank according to your requirement.
- By default, all data pins are contiguous in sequential order.
- For example, for a pin width of 8, data pins are assigned to Pin 0, 1, 2, and 3 in Lane 1 and Lane 2.
- You can choose to specify the placements manually, by providing a comma-separated list of pin locations, one for each data pin in Pin Placement Settings.
- The comma-separated list of pin locations is based on the index within an I/O sub-bank. Refer to the Pin Index Mapping table.
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