- Added information about Intel FPGA PHYLite for Parallel Interfaces in Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices.
- Added note to Reference Clock about using cascaded PLL as a reference clock in Intel® Arria® 10 devices and a link to the KDB.
- Rebranded to Intel FPGA PHYLite for Parallel Interfaces IP core.
- Added a note for the I/O Column for Arria 10 Devices figure.
- Updated Top-Level Interface diagram.
- Updated OCT section.
- Updated Guidelines: Group Pin Placement section.
- Updated the reference clock source in the Reference Clock section.
- Added Reset section.
- Added a note on Report DDR function in "<variation_name>_report_timing.tcl" section.
- Updated Altera PHYLite for Parallel Interfaces IP Core Parameter Settings table.
- Removed Use core PLL reference clock connection parameter.
- Added description for outclk (Reserved) parameter.
- Updated OCT enable size values and description.
- Added new parameter: Expose termination ports.
- Updated the description for ref_clk and interface_locked signals in the Clock and Reset Interface Signals table.
- Updated the description for data_in and data_io signals in Input Path Signals table.
- Rebranded as Intel.
- Removed 30 and 40 Ohms termination values for SSTL-125, SSTL-135, and SSTL-15 I/O standards.
- Added a footnote to I/O Standards table recommending to use I/O standards SSTL-15 Class I, SSTL-15 Class II, SSTL-18 Class I, SSTL-18 Class II, 1.2V HSTL Class I, 1.2V HSTL Class II, 1.5V HSTL Class I, 1.5V HSTL Class II, 1.8V HSTL Class I, and 1.8V HSTL Class II for interface frequency equal or less than 533 MHz and if input termination required.
- Added a footnote to I/O Standards table recommending to use I/O standards SSTL-12, SSTL-125, SSTL-135, and SSTL-15 for interface frequency more than 533 MHz and if input termination required.
- Added OCT section.
- Clarified that output terminations can be calibrated and uncalibrated in I/O Standards table.
- Added footnote to clarify that uncalibrated output terminations do not require RZQ pin in I/O Standard table.
- Clarified ONFI device support is for synchronous mode only.
- Updated Altera PHYLite for Parallel Interfaces IP Core supported Interface Frequency table.
- Clarified that reference clock using differential I/O standards support LVDS input buffer only.
- Updated I/O standards table with Valid Input Termination values.
- Added new guidelines to Group Pin Placement section.
- Updated Avalon Address for following features in the Address Map table:
- Pin PVT Compensated Input Delay
- Strobe PVT compensated input delay
- Strobe enable phase
- Added Altera PHYLite NAND Flash design example in Application Specific Design Example section.
- Removed IP Migration for Arria V, Cyclone V, and Stratix V section.
- Change External memory clock domain to Interface clock domain.
- Removed VCO Frequency Multiplication Factor table.
- Updated equation to calculate values for Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters.
- Updated Address Map table with values to enable Avalon address and CSR address.
- Added a note to show the location of the Altera PHYLite for Parallel Interfaces IP core in IP Catalog.
- Updated values for OCT enable size parameter.
- Added reference link to I/O Standards table in Data configuration parameter description.
- Added VCO clock frequency parameter in Parameter Settings table.
- Updated Minimum Read Latency and Maximum Write Latency tables.
- Updated PHYLite_delay_calculations.xlsx file.
- Added issp.tcl file description in Dynamic Reconfiguration with Debug Kit Design Example Generated Files table.
- Updated steps to generate Dynamic Reconfiguration with Debug Kit design example.
- Added functional description, simulation steps and result to Dynamic Reconfiguration with Configuration Control Module Design Example.
- Added Altera PHYLite for Parallel Interfaces IP Core Document Archives section.
- Changed Input Path Waveform figure label from "Intrinsic output delay at current in and out rates and frequency" to "Intrinsic input delay at current in and out rates and frequency".
- Added Altera PHYLite for Parallel Interface IP core uses cases.
- Clarified the condition for reference clock restriction in Reference Clock section.
- Added description for <variation_name>_parameter.tcl, <variation_name>_report_timing.tcl, and <variation_name>_report_parameter_core.tcl files into Timing Constrains and Files section.
- Provided example timing constraint command for increasing hold time uncertainty value.
- Added footnote to clarified functionality for DQS A and DQS B signals.
- Added new parameters in the Altera PHYLite for Parallel Interfaces IP Core Parameter Settings table:
- Copy parameters from another group
- OCT enable size
- Inter Symbol Interference of the Read Channel
- Inter Symbol Interference of the Write Channel
- Group <x> Dynamic Reconfiguration Timing Settings
- Added new dynamic reconfiguration with debug kit hardware example design.
- Added Write Latencies table in Parameter Settings.
- Updated Read Latencies table.
- Changed instances of Quartus II to Quartus Prime.
- Updated Avalon Address R/W from 3'h2 to 3'h4 for all features in Address Map table.
- Added new parameter Use core PLL reference clock connection and Data configuration in Altera PHYLite for Parallel Interfaces IP Core Parameter Settings table.
- Updated values in VCO Frequency Multiplication Factor table.
||Updated related information link to Functional Description for External Memory Interfaces in Arria 10 Devices.
- Updated the name of the IP core from Altera PHYLite for Memory to Altera PHYLite for Parallel Interfaces.
- Updated the maximum clock frequency from 800 MHz to 1333.333 MHz.
- Clarified that to achieve timing closure at 800 MHz and above, you must use dynamic reconfiguration to calibrate the interface.
- Added data_out_n/data_io_n signals to the Output Path Signals table.
- Added data_in_n/data_io_n signals to the Input Path Signals table.
- Updated data_out/data_io and data_in/data_io signals in the Input Path Signals and Output Path Signals tables.
- Updated Parameter Settings table to include Group <x> Timing Settings information.
- Updated Timing section to include Input Strobe Setup Delay Constrain and Input Strobe Hold Delay Constrain parameters information.
- Renamed the term megafunction to IP core.
- Added information about output path data alignment, input path data alignment, OCT, I/O standards, placement restrictions, timing, dynamic reconfiguration.
- Added the PHYLite_delay_calculations.xlsx file.
- Replaced ALTERA_PHYLite_nand_flash_example_131a10.qar file with nand_flash_example_14.0a10.qar file.