PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

Download
ID 683716
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.3.1. Output Path Data Alignment

The data_from_core and oe_from_core signals are arranged in time slices that are divided into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP.

Example of time slices with individual pins correlation:

{time(n),time(n-1),time(n-2),... time(0)}

Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}

Figure 65. Example Output for Quarter Rate DDR


Did you find the information on this page useful?

Characters remaining:

Feedback Message