PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide
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2.4.1. Input Buffer Reference Voltage (VREF)
The POD I/O standard allows configurable VREF. VREF range selection via QSF for POD 1.2 V requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE DDR4_CAL -to <pin_names>
set_instance_assignment -name VREF_MODE DDR4_CAL_RANGE2 -to <pin_names>
The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings including general-purpose I/Os (GPIO).
VREF Mode | Description |
---|---|
EXTERNAL | Use the external VREF. This is the default. |
DDR4_CAL | Use internal VREF generated using code set via dynamic reconfiguration. VREF range is 60%–92.5%. |
DDR4_CAL_RANGE2 | Use internal VREF generated using code set via dynamic reconfiguration. VREF range is 45%–77.5%. |