PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

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Document Table of Contents Input DQ/DQS Delay Chains Maximum Values

The complete range is from 0 to 551 in steps of T_vco/256, but the whole range is not always available. Also, only a portion of this range is usable depending on PLL frequency, temperature, and voltage. To find the usable range, perform the write and read-back operations to ensure if the value applies or needs to lower.

Assume the usable range has a maximum value of k and you write a value A. You can read back the value based on the following conditions:

  • If A < k, the value you write is under the upper limit, you read back the same value (readdata=A).
  • If A > k, the value you write is over the upper limit, you read back the upper limit value. (readdata=k).

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