126.96.36.199. Address Lookup
If you do not set the pin locations in the .qsf file, the lane addresses and pin placement to an interface changes every time you compile your design in Intel® Quartus® Prime software. However, the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP is always generated as if the IP core is the only IP in a column, with lane addresses starting from 0. You need to determine the lane and pin addresses in order to dynamically reconfigure the calibration settings in the IP.
To provide a unified way to look up reconfigurable feature addresses for a specific interface both before and after placement, the address information is stored in memory in the I/O column. This memory is addressable over the same Avalon memory-mapped interface used for feature reconfiguration.
You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane translations in one look-up.
|Global parameter table||Stores pointers to the individual interface parameter tables. The global parameter table lists all interfaces in the column (both the External Memory Interfaces and PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IPs).|
|Set of individual interface parameter tables||Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.|
Below are the steps to determine the lane and pin addresses from the lookup tables (the sequence corresponds to the sequence in the Memory Overview in Intel® Stratix® 10 Devices topic):
|Legend in Memory Overview in Intel® Stratix® 10 Devices||Description|
|1||Search for Interface Parameter Table in Global Parameter Table (cache once per interface)
|2||Retrieve number of groups in the interface (cache once per interface)
|3||Retrieve group information (cache once per group)
|4||Retrieve Lane/Pin Address Offsets for group (cache once per group)
|5||Perform lane/pin address translation (cache once per pin)
|6||Read/Write Avalon Calibration Bus
Did you find the information on this page useful?