PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
Public

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Document Table of Contents

1.2. Features

The PHY Lite for Parallel Interfaces IP:

  • Supports input, output, and bidirectional data channels.
  • Supports DQS-group based data capture, with up to 48 I/Os (including data, strobes, PLL reference clock) per IP for Intel® Agilex™ devices and 48 I/Os (including strobes) per group for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
  • Supports DQS gating/ungating circuitry for strobe-based interfaces.
  • Supports output delays via interpolator.
  • Supports dynamic on-chip termination (OCT) control.
  • Supports quarter-rate for Intel® Agilex™ devices and quarter-rate to half-rate and half-rate to full-rate of the interface clock conversions for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
  • Supports input, output, and read/DQS/OCT enable paths.
  • Supports single data rate (SDR) and double data rate (DDR) at the I/Os.
  • Supports PHY clock tree.
  • Supports dynamically reconfigurable delay chains using Avalon® memory-mapped interface for Intel® Agilex™ , Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
  • Supports process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
    Note: The non-PVT compensated component of the input delay is set through the .qsf assignment in the Intel® Quartus® Prime software.

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