PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
Public

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4.5.5. Dynamic Reconfiguration

If you are using the dynamic reconfiguration feature, all interfaces of the External Memory Interfaces and PHY Lite for Parallel Interfaces IP cores in the same I/O column must share the reset signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity.

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