PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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2.2.4.2. Reconfiguration Features and Register Addressing

Each reconfigurable feature of the interface has a set of control registers with an associated memory address to store the reconfigurable settings; however, this address is placement dependent. If PHY Lite for Parallel Interfaces IPs and the External Memory Interface IPs share the same I/O column, you must track the addresses of the interface lanes and the pins.

The following two sets of control registers store the reconfiguration feature settings:

  • Control/status registers (CSR)—You can only read the values of these registers. The values are set through the IP parameters. The CSR registers contain the default setting in the IP.
  • Avalon® memory-mapped registers—You can read and write to these registers using Avalon® interface. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.

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