Visible to Intel only — GUID: rkd1606745079567
Ixiasoft
Visible to Intel only — GUID: rkd1606745079567
Ixiasoft
2.2.4.2. Reconfiguration Features and Register Addressing
Each reconfigurable feature of the interface has a set of control registers with an associated memory address to store the reconfigurable settings; however, this address is placement dependent. If PHY Lite for Parallel Interfaces IPs and the External Memory Interface IPs share the same I/O column, you must track the addresses of the interface lanes and the pins.
The following two sets of control registers store the reconfiguration feature settings:
- Control/status registers (CSR)—You can only read the values of these registers. The values are set through the IP parameters. The CSR registers contain the default setting in the IP.
- Avalon® memory-mapped registers—You can read and write to these registers using Avalon® interface. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.
Did you find the information on this page useful?
Feedback Message
Characters remaining: