PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

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Document Table of Contents <variation_name>_report_timing.tcl

The <variation_name>_report_timing.tcl file is a script that contains timing analysis flow and reports the timing slack for your variation. This script runs automatically during calibration (during static timing analysis) by sourcing the following files:
  • <variation_name>_ip_parameters.tcl
  • <variation_name>_parameters.tcl
  • <variation_name>_pin_map.tcl
  • <variation_name>_report_timing_core.tcl
You can also run <variation_name>_report_timing.tcl with the Report DDR function in the Timing Analyzer. This script runs for every instance of the same variation.
Note: You can only use the Report DDR function if you enable the dynamic reconfiguration feature.