220.127.116.11. Manual Insertion of OCT Block
You may also instantiate the OCT Intel FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces.
- Expose the PHY Lite for Parallel Interfaces termination ports by disable Use Default OCT Values.
- Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
- Select Expose termination ports to expose the termination ports in the IP.
- Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.
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