PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

Download
ID 683716
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.2. Functional Description

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP utilizes the I/O banks in Intel® Agilex™ devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.

Each each sub-bank contains the following components:

  • Hard memory controller
  • I/O PLL and PHY clock trees
  • DLL
  • Input DQS/strobe trees
  • 48 pins, organized into four I/O lanes of 12 pins each
Figure 1.  Intel® Agilex™ I/O Bank Structure

Did you find the information on this page useful?

Characters remaining:

Feedback Message