PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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4.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avalon interface returns a set of values from the control registers. The following tables show the definition of the bits for each control register.
Table 73.  Control Register Description
Feature Bit Description
Pin Output Delay [31:13]

Reserved 11

[12:0]

Phase value

Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation.

Note: The pin output delay switches from the CSR register value to the Avalon register value after the first Avalon write. It is only reset to the CSR register value on a reset of the interface.
Pin Input Delay [31:13]

Reserved 11

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register

[11:9] Reserved 11
[8:0]

Delay value

Minimum Setting: 0

Maximum Setting: 511 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13]

Reserved 11

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[11:10] Reserved11
[9:0]

Delay value

Minimum Setting: 0

Maximum Setting: 1023 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Modifying these values must be done on all lanes in a group.

Strobe Enable Phase [31:16] Reserved 11
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[14:13] Reserved11
[12:0]

Bit [12:0]: Phase value

Minimum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Maximum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

Modifying these values must be done on all lanes in a group.

Strobe Enable Delay [31:16] Reserved11
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[14:6] Reserved11
[5:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 63 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.

Read Valid Delay [31:16] Reserved11
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.

[14:7] Reserved
[6:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 127 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.

Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.
11 Reserved bit ranges must be zero

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