PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

Download
ID 683716
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.1.2. Write Latency

Table 14.  Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate VCO Multiplier Factor Write Latency (External Memory Clock Cycle)
Quarter rate 1 3
2 3
4 3
8 2

Did you find the information on this page useful?

Characters remaining:

Feedback Message