PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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3.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.

  1. Expose the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP termination ports by disable Use Default OCT Values.
  2. Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
    Note: For supported input and output OCT values, refer to the I/O Standards topic.
  3. Select Expose termination ports to expose the termination ports in the IP.
  4. Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.
Figure 48. RTL View of PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP Interfacing with OCT Intel FPGA IP in User Mode

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