PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2. Functional Description

The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP utilizes the I/O subsystem in the Intel® Stratix® 10 devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel® Stratix® 10 devices, each column consists of I/O banks and IOSSM. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank. Refer to the Guidelines: Group Pin Placement for more information about the guidelines to implement multiple interfaces in the same bank.

Important: All Intel® Stratix® 10 devices have separate LVDS I/O and 3 V I/O banks. The Intel® Stratix® 10 GX 10M variant has denser LVDS I/O banks with a slightly different I/O bank structure compared to other Intel® Stratix® 10 variants. The PHY Lite for Parallel Interfaces IP utilizes only the LVDS I/O banks.
Figure 28.  Intel® Stratix® 10 I/O Bank StructureThis figure shows an example of I/O banks in one Intel® Stratix® 10 device. The I/O banks availability and locations vary among Intel® Stratix® 10 devices.