18.104.22.168. Timing Analysis
|I/O|| The PHY Lite for Parallel Interfaces IP generation creates the appropriate generated clock settings for the read strobe on the read path and the write strobe of the write path, according to their strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the following format:
|FPGA|| The PHY Lite for Parallel Interfaces IP generation creates the clock settings for the user core clock and the periphery clock in the following formats:
The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel Interfaces IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing of this IP interface transfer and within core transfer correctly.
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