PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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3.5.6.3. Timing Analysis

Table 53.  Timing AnalysisThis table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces IP.
Location Description
I/O The PHY Lite for Parallel Interfaces IP generation creates the appropriate generated clock settings for the read strobe on the read path and the write strobe of the write path, according to their strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the following format:
  • Clock name for read strobe—<pin_name>_IN.
  • Clock name for the write path—<pin_name> for positive strobe.
  • Clock name for the write path—<pin_name>_neg for negative strobe.
The set_false_path, set_input_delay and set_output_delay constraints are also generated to ensure proper timing analysis of the PHY Lite for Parallel Interfaces IP.
FPGA The PHY Lite for Parallel Interfaces IP generation creates the clock settings for the user core clock and the periphery clock in the following formats:
  • user core clock— <variation_name>_usr_clk
  • periphery clock— <variation_name>_phy_clk*

The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel Interfaces IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing of this IP interface transfer and within core transfer correctly.

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