PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
Public

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2.2.4.1. Connectivity

The PHY Lite for Parallel Interfaces IP exposes the Avalon® memory-mapped interfaces when you enable the dynamic reconfiguration feature. The connectivity of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP to the Avalon® memory-mapped interfaces must be performed via Calibration IP. One Calibration IP must be shared across different PHY Lite for Parallel Interfaces IPs within the same row. For example, all IPs in the bottom row are connected to one Calibration IP and all IPs in the top row are connected to another Calibration IP. This Calibration IP does not perform any calibration for the PHY Lite for Parallel Interfaces IP. The Calibration IP only provides an access path ( Avalon® memory-mapped bus) to all the registers of interest for reconfiguration.

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